ASIC verification engineer

  • Full Time
  • Brasov
  • This position has been filled

ASIC verification engineer


Integrating verification environments for block sand subsystems within the verification system environment. The verification engineer will be in charge of developing and integrating verification components, of developing a test plan based on specifications, of writing and running tests and analyzing errors.
 Test planning, developing applications and scripts necessary to enable the automatic verification within the system.
 Collaborating with the systems’ IPs development teams.
 Active contribution to the joint effort of verification of a complex chip, subsystem or block.


MUST have:
 Verilog
 Very good English
 Good technical capabilities
 Good communication skills
NICE to have
 Software skills with experience using System Verilog/UVM
 Skills in RTL debugging
 Test plans creating
 Previous experience in SoC

Beneficii Oferite

 Relocation package

 Salary above average

 Unlimited employment contract

 No probation period

 Increasing number of vacation days upon experience in the company

 Sport activities sponsorship

 Team building activities

 Travel opportunities

Please send your resumes at the following address:

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Author: admin